Senior ASIC Design Verification Engineer - Slingshot

Senior ASIC Design Verification Engineer - Slingshot

This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work.

We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.

Our culture thrives on finding new and better ways to accelerate what's next.

We know varied backgrounds are valued and succeed here.

We have the flexibility to manage our work and personal needs.

We make bold moves, together, and are a force for good.

If you are looking to stretch and grow your career our culture will embrace you.

Open up opportunities with HPE.

Job Description:

In this role you will be responsible for all phases of pre-silicon design verification, including design verification methodology, test-plan development, testbench development, coverage closure, and sign-off reviews.

Responsibilities


* Follow and help define the team's design verification methodology.


* Develop SystemVerilog and UVM testbench components, including bus functional models that drive and monitor stimulus.


* Plan and implement block and integration level scoreboards and checkers to verify functional behavior.


* Write and analyze functional coverage, providing input to block level milestones.


* Triage regression failures and identify logic bugs, while driving bug closure.


* Apply scripting, automation, and AI-assisted and agentic tools to improve the speed and quality of the verification process.


* Provide guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence.


* Participate in and provide input on the process for selection of future technical leaders.


* Drive VLSI innovation and integration of new technologies into projects and activities in the design organization.

Education and Experience Required


* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.


* 10+ years of experience in VLSI design, verification, or implementation.

Knowledge and Skills


* Expert level knowledge of SystemVerilog and of OVM or UVM methodologies.


* Expert level knowledge of programming and scripting languages, hardware description languages, electronic design automation (EDA), and/or FPGA tools.


* Expert level analytical and problem solving skills.


* Ability to excel in a distributed team environment.


* Executive level written and verbal communication skills; mastery in English.

Preferred Skills


* Experience verifying high-speed networking, switching, or NIC ASICs.


* Experience with agentic AI coding tools and workflows applied to verification.
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