Sr. ASIC Physical Design Engineer

Sr.

ASIC Physical Design Engineer

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work.

We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.

Our culture thrives on finding new and better ways to accelerate what's next.

We know varied backgrounds are valued and succeed here.

We have the flexibility to manage our work and personal needs.

We make bold moves, together, and are a force for good.

If you are looking to stretch and grow your career our culture will embrace you.

Open up opportunities with HPE.

Job Description:

As a block-level Physical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII.

Your responsibilities include:

Responsibilities:



* Implement physical design at the large SoC block level from RTL to GDSII, creating a design database ready for manufacturing.



* Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub - chips at a large SoC level.



* Collaborate with the packaging team on Microbump / Probe Bump/ Bump/Pad placement.



* Build block level floorplan, including block pins, macro placement and alignment, power grid , etc.



* Develop the block-level clock network and clock structure in collaboration with clock experts.



* generating block/chip-level static timing constraints.



* Arrange, analyze, and optimize feedthrough and repeaters among all blocks



* Perform block-level place and route, including custom place & route, ensuring the design meets timing, area, power constraints, and all sign-off criteria.



* Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.



* Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.



* Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.



* Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts .

Minimum Qualifications:

Education:



* BS degree in electrical engineering, computer engineering, or a related field with 3+ years of experience in block or full-chip physical design, or



* MS degree in the above fields with 2+ years of related experience.

Technical Expertise:



* Deep design experience in large SoC designs, including IP integration.



* Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/fee...