Principal VLSI Design Engineer, Sunnyvale, CA

Principal VLSI Design Engineer, Sunnyvale, CA

This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work.

We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.

Our culture thrives on finding new and better ways to accelerate what's next.

We know varied backgrounds are valued and succeed here.

We have the flexibility to manage our work and personal needs.

We make bold moves, together, and are a force for good.

If you are looking to stretch and grow your career our culture will embrace you.

Open up opportunities with HPE.

Job Description:

Principal VLSI / ASIC Design Engineer (Networking ASICs)

Role Summary

You will architect, design, and implement complex networking ASICs.

You will create chip‑level and block‑level architecture and micro‑architecture, write high‑quality RTL, and work closely with verification and physical design teams to deliver clean, efficient, and high‑performance silicon.

US Citizenship preferred

Location: Sunnyvale, CA

Onsite work required weekly 2 days per week; Tuesdays and Thursdays

Responsibilities


* Define ASIC architecture for networking chips, including data paths, packet processing, control logic, memory structures, and interfaces.


* Develop detailed micro‑architecture for complex blocks and ensure they meet functional and performance goals.


* Write clear, efficient, synthesizable RTL (SystemVerilog/Verilog) for the designed blocks.

Create assertions and assist in functional coverage


* Work closely with verification engineers to ensure the RTL is fully tested, bug‑free, and meets all functional requirements.


* Provide guidance to the verification team on test plans, coverage goals, corner cases, and expected behavior.


* Collaborate with physical design engineers to ensure the design meets timing, area, and power targets.


* Review synthesis, timing, and power reports, and update RTL or micro‑architecture as needed.


* Participate in design reviews, provide clear feedback, and ensure compliance with design guidelines.


* Support integration and debug during simulation, emulation and silicon bring‑up.


* Identify technical risks early and propose simple, effective solutions.

Knowledge & Skills


* Strong understanding of ASIC architecture and micro‑architecture.


* Strong background in networking ASICs (switching, routing, packet processing, or similar preferred).


* Expert in RTL coding in Verilog or SystemVerilog, assertions and functional coverage


* Strong knowledge of digital design fundamentals, pipelining, clocking, resets, FIFOs, arbiters, and data path design.


* Experience working with...