Principal Physical Design Engineer

Principal Physical Design Engineer

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work.

We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.

Our culture thrives on finding new and better ways to accelerate what's next.

We know varied backgrounds are valued and succeed here.

We have the flexibility to manage our work and personal needs.

We make bold moves, together, and are a force for good.

If you are looking to stretch and grow your career our culture will embrace you.

Open up opportunities with HPE.

Job Description:

Job Description: Physical Design Flow and P&R Development Engineer (Innovus / Fusion Compiler)

Role Overview

We are seeking a highly skilled Physical Design Flow and Place‑and‑Route (P&R) Development Engineer to drive methodology, automation, and implementation solutions for advanced ASIC designs.

The ideal candidate will have deep experience with Cadence Innovus, Synopsys Fusion Compiler, and modern RTL‑to‑GDS flows.

This role focuses on developing scalable P&R methodologies, improving flow robustness, and partnering with design teams to deliver high‑quality, high‑performance silicon.

Key Responsibilities

P&R Flow Development & Methodology (Main Responsibility)


* Develop, maintain, and enhance RTL‑to‑GDS flows using Innovus and Fusion Compiler.


* Create robust, repeatable methodologies for floorplanning, placement, CTS, routing, and optimization.


* Automate flow steps using Tcl, Python, and Makefile‑based infrastructures.


* Investigate and deploy new tool features, optimization techniques, and technology‑node‑specific capabilities.

Physical Design Support


* Partner with RTL designers, analog/mixed‑signal teams, and PD implementers to support full‑chip and block‑level P&R execution.


* Provide hands‑on support for floorplan definition, clock topology, power grid planning, placement optimization, timing closure, IR/EM mitigation, and DRC fixing.


* Debug tool issues, convergence challenges, and signoff discrepancies across STA, LVS, DRC, and extraction.

Implementation Quality & Signoff


* Ensure P&R flows achieve best‑in‑class results on timing, area, power, noise, and DRC.


* Drive correlation improvements between FC/Innovus and signoff tools (PrimeTime, StarRC, Voltus, RedHawk, Calibre).


* Define and enforce physical signoff criteria and quality metrics.

Cross‑Team Collaboration


* Interface with EDA, library/PDK, signoff, and architecture teams to support technology bring‑up and design scalability.


* Help evaluate new EDA tools, PDK features, and design methodologies for nex...