ASIC Verification Engineer

ASIC Verification Engineer

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work.

We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.

Our culture thrives on finding new and better ways to accelerate what's next.

We know varied backgrounds are valued and succeed here.

We have the flexibility to manage our work and personal needs.

We make bold moves, together, and are a force for good.

If you are looking to stretch and grow your career our culture will embrace you.

Open up opportunities with HPE.

Job Description:

HPE Networking is a leading provider of advanced routers and switches for the internet.

We keep the world connected with speed, reliability, security, and ease of use.

At HPE networking Silicon group, we push the boundaries of what is possible in a piece of silicon die.

We build cutting edge networking chips used to build world-class routers and switches.

Bring your passion and there are no boundaries to what you can accomplish here.

We are like a start-up in a big company.

Year after year, our group builds the most powerful and highest density networking chips.

As part of our fast-paced chip design group, you will become an expert in building/validating high-speed ASICs.

We give you opportunities to work on complex blocks where you can challenge yourself and grow.

Open communications, empowerment, innovation, teamwork, and customer success are the foundations of the team.

Thus, you set your own limits for learning, achievements, and rewards.

Responsibilities:


* You will be exposed to the latest verification methodologies such as UVM and you will enable complex feature verification suites.


* You will start with a functional specification of a module and produce a detailed test plan to verify the module.


* You will write functional models for the module using System Verilog/C/C++ for architectural validation.


* You will build the module level test bench using System Verilog/UVM


* You will write tests according to the test plan and find bugs in the module.

You will be responsible for making sure your module is fully functional.


* You will work closely with logic designers to resolve bugs, with SW engineers to assist in driver code development.


* You will use state of the art tools for doing formal verification, code coverage analysis, gate sims, and more.


* You will also get a chance to be part of full chip/sub-system and emulation testing - which gives you exposure to the entire functionality of the chip/system.


* You get to participate in ASIC validation in the lab if you are passionate about making the chip come alive.


* You wil...