ASIC Engineer Sr Staff

ASIC Engineer Sr Staff

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work.

We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.

Our culture thrives on finding new and better ways to accelerate what's next.

We know varied backgrounds are valued and succeed here.

We have the flexibility to manage our work and personal needs.

We make bold moves, together, and are a force for good.

If you are looking to stretch and grow your career our culture will embrace you.

Open up opportunities with HPE.

Job Description:

About HPE Networking:

At HPE Networking, we are redefining the future of high-performance networking.

Our silicon team is at the forefront of innovation, developing cutting-edge ASICs for next-generation networking platforms.

We are looking for a seasoned

Design-for-Test (DFT) Engineer to join our team and contribute to the development of advanced 3nm and beyond networking silicon.

Job Summary:

As a DFT Engineer at HPE Networking, you will play a critical role in ensuring the testability and reliability of our high-speed, high-complexity ASICs.

You will work closely with front-end design, physical design, and verification teams to architect and implement robust DFT solutions that meet stringent performance and quality requirements.

Key Responsibilities:


* Define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond.


* Collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features.


* Develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models.


* Analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations.


* Apply test constraints and perform STA analysis to ensure timing closure in test modes.


* Support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF).


* Conduct silicon failure analysis and contribute to system-level debug and yield improvement.


* Automate DFT flows and analysis using scripting languages such as Perl and Tcl.

Required Skills & Experience:


* 10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains.


* Deep understanding of fault models: stuck-at, transition, path-delay.


* Expertise in scan compression, ATPG, and MBIST architecture.


* Experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair.


* Proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler.


* Simulation experience with Synopsys VCS an...